A Novel Mixed Signal Programmable Device with On-chip Microprocessor

In this paper we present a novel field programmable mixedsignal integrated device consisting of a Field Programmable Gate Array (FPGA), a set of programmable and interconnectable analog cells, and a microprocessor core. This processor can run general purpose user programs, handle the dynamic reconfiguration of the programmable blocks and probe in real time internal digital and analog signals. The device is especially suitable for development and fast prototyping of mixed signal integrated applications. Introduction As the complexity of electronic systems grows, it becomes more and more difficult to follow a traditional design methodology of working separately on different subsystems with different design and prototyping tools. System designers have been craving for flexible prototyping systems onto which they could map large designs to validate them before fabrication. Typically, these designs may include a digital part, an analog part and a software program running on a microprocessor or microcontroller. However, these three domains (digital, analog and software) have to be designed and prototyped separately, using different CAD tools and hardware parts for each one. Besides FPGAs, only recently analog arrays have been available (1) (2), which confirms the interest shown by the industry for fieldprogrammable devices suitable for fast prototyping and small time to market applications. Within this framework we introduce the FIPSOC (FIeld Programmable System On Chip) prototyping and integration system, consisting of a mixed-signal Field Programmable Device (FPD) with a standard microprocessor core (a 8051), a suitable set of CAD tools to easily program it, and a set of library macros and cells which support a number of typical applications to be easily mapped onto the FPD and migrated to an ASIC afterwards, if required. The advantage of this approach relies upon the fully integrated design and prototyping methodology that the user can follow with such a system, because he can download his application onto the programmable hardware and then use the internal microcontroller to probe it in real time (both digital and analog). A powerful integrated set of userfriendly CAD tools is provided, with the final target of letting the user specify, simulate, emulate (probe in real time) and map the complete design on to a single chip using one design environment. Also, a suitable library has been developed providing a very easy path for migration to ASIC after the prototyping phase. The FIPSOC project is still under development, and will provide a complete family of devices comprising a number of different sizes and models. Only worst case simulation results from the first familiy member will be given. This paper is mainly focused on the FIPSOC chip architecture and is organized as follows. The following section describes the circuit in its three parts (digital hardware, analog cells and microprocessor core and interface). Next, we explain how the multicontext dynamic reconfiguration works in this device and how it can be applied to hardware-software interaction. Then, we describe how this system can be used as a prototyping workbench with real time probing. Finally, we give some ideas about the CAD tools being developed to manage this chip. System Description Fig. 1 shows a block diagram of the FIPSOC device. Fig.1: Block diagram of the FIPSOC chip The chip is a mixed signal field programmable device with an on-chip microcontroller. It includes a Field Programmable Gate Array (FPGA), a set of fixedfunctionality yet configurable analog cells, and a microprocessor core with RAM memory and some peripherals. The programmable digital and analog blocks are well defined and are separated from one another due to noise inmunity considerations. Nevertheless, the different interfaces between these blocks themselves and to the microprocessor provide a very powerful interaction between software, digital hardware and analog hardware. The chip has been designed using a full custom methodology for the FPGA and the analog area, and a synthesized soft core for the microcontroller. A 0.5μm triple metal layer CMOS 3V process provided by ATMEL ES2 was chosen to implement the first generation of this device. In the next paragraphs we describe separately the programmable digital cells (the FPGA), the configurable analog blocks, and the microcontroller. Finally, we talk about the interfaces between these three blocks. A. Programmable Digital Hardware The FIPSOC chip includes a two-dimensional array of programmable DMCs (Digital Macro Cell). The DMC is a large granularity, Look Up Table (LUT) based, synthesis targeted 4-bit wide programmable cell. Fig. 2 shows a simplified block diagram of the DMC.